1. Field of the Invention
The present invention generally relates to an output buffer with good electrostatic discharge protection. More specifically, the present invention relates to an output buffer which prevents voltage ringing and overshooting and apart from providing good electrostatic discharge protection.
2. Description of the Related Art
When an integrated circuit (i.e. IC) is located on a mother board, the CMOS I/O buffer can have large shooting and overshooting due to the wiring capacitance and inductance from the IC package and wiring of mother board. Traditionally, an external resistor in the order of 10 ohms can be soldered to a mother board next to a CMOS I/O pin, thus providing a series resistor to dampen the voltage ringing and overshooting, as shown in FIG. 1A. In FIG. 1A, CMOS I/O buffer 2 comprises an output buffer 3, a secondary ESD protection circuit 4 and an input buffer 5. Wherein, output buffer 3 comprises a pull up PMOS P1 and a pull down NMOS N1. Because output buffer 3 needs to provide a large driving ability, both PMOS P1 and NMOS N1 have gate widths wide enough, such that they can act as a main ESD protection circuit. Secondary ESD protection circuit 4, as shown in FIG. 1A, comprises a 200 ohms resistor coupled between input buffer 5 and PAD 10 to minimize the effect of ESD on input buffer 5. Hence, PMOS P2 and NMOS N2 for dissipating the ESD current are miniaturized to be smaller than output buffer 3. The externally connected resistor 7 increases the load of output buffer 3 and suppress the voltage ringing and overshooting caused by wiring capacitance and inductance from the IC package. However, the participation of an extra part, such as resistor 7, is extravagant in view of motherboard integration. It increases the total area of motherboard and the complexity of part management. Thus the design in FIG. 1A is not well considered.
Another method for suppressing voltage ringing and overshooting is by removing the external resistor 7, and adding two on-chip resistors in series with the PMOS P1 and NMOS N1 respectively, as shown in FIG. 1B. Thus, pull up PMOS p1 is provided with a resistor Rp, pull down NMOS is provided with a resistor Rn. The driving ability of I/O buffer is hence diminished by the addition of the two resistors Rn and Rp. Thus the voltage ringing and overshooting at the pad will be smaller. The larger resistance values of resistors Rn and Rp, the better its damping effect on voltage ringing and overshooting. However, the resistance of Rn and Rp should not be so large that the driving ability cannot meet the requirement of the CMOS I/O buffer. For example, the required driving ability of the NMOS N1 is to drain a DC current of about 8 to 10 mA and a maximum transient current of about 40 mA, further with a specification of voltage overload (VOL) about 0.4 V. In order to comply with the limit of the VOL specification, the resistance of resistor Rn cannot be more than 10 ohms. The resistor Rn of 10 ohms contributes a voltage drop of 0.1 volt when the NMOS drains the DC current of 10 mA. Thus the pull down circuit can comply with the VOL specification.